A Hybrid Compensation Scheme for the Gate Drive Delay in CLLC Converters

The CLLC converter is often used as an isolated linker between high- and low-voltage buses where the operates under open-loop condition at a resonant frequency. In such applications, converters are able to achieve high efficiency usually due superior performance of soft switching. However, we found that operating process control frequency will significantly change by nonideal parameters semiconductor switches gate driver circuits. These impacts on operation were investigated defined drive delay. We present comprehensive steady-state analysis for considers delay including its process, mathematical model, power loss, voltage ripple. some cases, changes converter. As result, soft-switching or even loses, large circulating current exists secondary side, output ripples become larger, so decreases dramatically. Therefore, hybrid compensation scheme, consisting offline design procedure online closed-loop algorithm, proposed minimize resonant-frequency variation Both correctness effectiveness scheme verified experiment. Using can reduce ripple one-third original value increase more than 10% within whole load range.